1. Field of the Invention
The present invention relates to an electronic device package, and to an electronic equipment.
Priority is claimed on Japanese Patent Application No. 2004-331962, filed Nov. 16, 2004, the content of which is incorporated herein by reference.
2. Description of Related Art
From the past, as a technique for mounting an electronic device such as a semiconductor chip (an IC chip) or the like upon a substrate, in order electrically to connect together a terminal electrode on one surface of the electronic device (a device electrode) and a wiring pattern upon the substrate, the so called wire bonding technique has been widely used (for example, refer to Japanese Unexamined Patent Application, First Publication No. 2004-221257).
Apart from this technique, as a technique related to the above described electrical connection, there is a technique in which an electrically conductive member is sandwiched between the terminals which are to be the object of connection (for example, refer to Japanese Unexamined Patent Application, First Publication No. 2000-216330). Furthermore, as a technique directed to the same objective, there is a technique in which a member which includes anisotropic electrically conductive particles (an anisotropic electrically conductive film (ACF) or an anisotropic electrically conductive paste (ACP)) is placed between electrodes which are arranged so as to confront one another (for example, refer to Japanese Unexamined Patent Application, First Publication No. 2000-068694).
Yet further, in relation to the above described electrical connection, a technique has been proposed which utilizes a liquid drop ejection method (for example, refer to Japanese Unexamined Patent Application, First Publication No. 2004-281539). In this technique, an electrically conductive material is placed upon the substrate in liquid drop form, and the connecting wiring is formed by hardening this material.
This technique for forming connecting wiring using the above described liquid drop ejection method possesses the beneficial aspect that the stress which is imposed upon the electronic device during the process of wiring formation is comparatively small. Moreover, with the above described technique, it is easy to plan for reduction of the pitch (i.e., miniaturization) of the wiring, since it is possible to arrange the material with high accuracy.
However, even if the pitch of the terminal electrodes upon the electronic device is narrowed down, it often happens that the pitch of the wiring upon the substrate (the substrate electrode) cannot correspond thereto. In other words, due to various limitations, there is a tendency for the lower limit value for the array pitch of the electrodes upon the substrate to be large, as compared with that for the electrodes upon the electronic device. This fact can easily lead to increase of the size of the wiring region upon the substrate, due to the requirements for extending the wiring and the like, and this can constitute a hindrance to making the substrate more compact.